	//================================================
//  Company     : ICDREC
//  Project     : SG8
//  File name   : tmr3_top.v
//  Author      : Nguyễn Việt
//  Date        : August 05th 2014
//  Version     : 
//-------------------------------------------------
// Modification History
// Date: 	By: 
// - 
//=================================================
module tmr3_top(
				//clock and reset
				gclk_tmr3,
				reset_n,
				//inputs
				bus_tmr3_sel,
				bus_tmr3_we,
				bus_addr,
				bus_wdata,
				tmr3_cnt_ev,
				tmr3_cap_ev,
				int_tmr_cnt_we,
				int_tmr_cnt_wdata,
				int_cap_cmp_we,
				int_cap_cmp_wdata,
				//outputs
				tmr3_int,
				tmr3_cap_cmp_int,
				tmr3_on,
				tmr3_cmp_out,
				tmr3_rdata
				);
	
	input 			gclk_tmr3;
	input 			reset_n;
	input 			bus_tmr3_sel;
	input 			bus_tmr3_we;
	input 	[3:0]	bus_addr;
	input 	[7:0]	bus_wdata;
	input 			tmr3_cnt_ev;
	input 			tmr3_cap_ev;
	input 			int_tmr_cnt_we;
	input 			int_tmr_cnt_wdata;
	input 			int_cap_cmp_we;
	input 			int_cap_cmp_wdata;	
	output 			tmr3_int;
	output 			tmr3_cap_cmp_int;
	output 			tmr3_cmp_out;
	output 	[7:0]	tmr3_rdata;
	output			tmr3_on;
	//internal wires and registers
	wire 			set_tmrif;
	wire 	[5:0] 	tcon;
	wire 	[5:0] 	sca;
	wire 			set_cmpif;
	wire			set_capif;
	wire 	[23:0] 	t3cnt;
	wire 	[23:0] 	cmp;
	wire			cnt_en;
	wire			tmr3_on;
	wire			t3cnt_en;
	tmr3_read_write read_write(
								.gclk_tmr3(gclk_tmr3),
								.reset_n(reset_n),
								.bus_tmr3_sel(bus_tmr3_sel),
								.bus_tmr3_we(bus_tmr3_we),
								.bus_addr(bus_addr[3:0]),
								.bus_wdata(bus_wdata),
								.int_tmr_cnt_we(int_tmr_cnt_we),
								.int_tmr_cnt_wdata(int_tmr_cnt_wdata),
								.int_cap_cmp_we(int_cap_cmp_we),
								.int_cap_cmp_wdata(int_cap_cmp_wdata),
								.tmr3_int(tmr3_int),
								.tmr3_cap_cmp_int(tmr3_cap_cmp_int),
								.tmr3_rdata(tmr3_rdata[7:0]),
								.set_tmrif(set_tmrif),
								.set_cmpif(set_cmpif),
								.set_capif(set_capif),
								.t3cnt(t3cnt[23:0]),
								.tcon(tcon[5:0]),
								.sca(sca[5:0]),
								.cnt_en(cnt_en),
								.cmp(cmp),
								.tmr3_on(tmr3_on),
								.t3cnt_en(t3cnt_en)
								);	
	tmr3_timer_counter timer_counter(
									.gclk_tmr3(gclk_tmr3),
									.reset_n(reset_n),
									.tmr3_cnt_ev(tmr3_cnt_ev),
									.set_tmrif(set_tmrif),
									.tcon(tcon[1:0]),
									.sca(sca[5:0]),
									.t3cnt(t3cnt[23:0]),
									.tmr3_int(tmr3_int),
									.cnt_en(cnt_en),
									.tmr3_on(tmr3_on),
									.t3cnt_en(t3cnt_en)
									);
	tmr3_cap_cmp cap_cmp(
							.gclk_tmr3(gclk_tmr3),
							.reset_n(reset_n),
							.tmr3_cap_ev(tmr3_cap_ev),
							.tmr3_cmp_out(tmr3_cmp_out),		
							.tcon(tcon[5:0]),
							.t3cnt(t3cnt[23:0]),
							.cmp(cmp[23:0]),
							.set_capif(set_capif),
							.set_cmpif(set_cmpif),
							.cnt_en(cnt_en),
							.tmr3_on(tmr3_on)
							);
endmodule
	
	
	
	
	
	
	
	
	
		
	
